Ed, Drew and all,
Puget Systems is a successful custom computer build company for nearly 20 years. I have not been a customer of theirs, but respect the information which they share.
I found a late 2013 article on their website which appears to summarize ECC memory clearly, concisely and fairly. The article is at:
https://www.pugetsystems.com/labs/articles/Advantages-of-ECC-Memory-520/In summary:
- ECC stands for Error Correction Code memory
- ECC memory protects against data corruption by automatically detecting and correcting memory errors
- ECC memory adds 1 memory chip to standard non-ECC memory's 8 memory chips on a memory card
- ECC generates a 7 bit code for each 64 data bits in memory
- on a 64 data bit read, a 2nd 7 bit code is generated and compared with the original 7 bit code
- if the two 7 bit codes match, then no errors
else the ECC memory system finds which bits are in error by comparing the two 7 bit code, then fixes the error'd data bits
ECC and non-ECC failure comparison
- In 2011, Kingston ECC failed .53% and Non-ECC failed 1.16%
- In 2012, Kingston ECC failed .19% and Non-ECC failed .93%
- In 2013, Kingston ECC failed .00% and Non-ECC failed .83%
- As of late 2013, their testing of non-ECC memory dropped their failure rate from about 1% to about .4%.
- Most desktop systems won't work with ECC memory or ECC functionality is disabled.
- Most server and workstation motherboards require ECC memory.
- ECC memory costs 10-20% more than non-ECC memory.
- ECC memory can be .72% to 2.2% slower than non-ECC memory.
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Alternatively, a way to be more confident of non-ECC memory is to extensively test each memory card.
MemTest86 (
https://www.memtest86.com/index.html) has a free memory testing tool which I have used periodically for more than 15 years. MemTest86 has 13 different tests (for example: address tests, moving inversions tests, block move). MemTest86 also includes a test for Row Hammer errors (a common memory error defect).
From:
https://www.memtest86.com/tech_individual-test-descr.html:
The row hammer test exposes a fundamental defect with RAM modules 2010 or later. This defect can lead to disturbance errors when repeatedly accessing addresses in the same memory bank but different rows in a short period of time. The repeated opening/closing of rows causes charge leakage in adjacent rows, potentially causing bits to flip.
This test 'hammers' rows by alternatively reading two addresses in a repeated fashion, then verifying the contents of other addresses for disturbance errors. For more details on DRAM disturbance errors, see Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors by Yoongu Kim et al.
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My long term MemTest86 experience has been - any of my memory cards (non-ECC or ECC) which has passed MemTest86, has not failed subsequently.
As you can see, both non-ECC memory passing MemTest86 tests and ECC memory could be options to reduce errors, particularly for public performance Hauptwerk systems.
Mark